1. Field of the Invention.
This invention relates in general to timing analysis and verification tools for electrical circuits, and in particular to a computer program which automates the entry, modification, and analysis of timing diagrams.
2. Description of Related Art
Timing diagrams are a traditional type of chart that engineers use to describe the proper sequence and order of events in a circuit, including timing dependencies and relationships. Typically, the task of timing analysis and verification is done manually using paper and pencils.
Events in digital circuits are usually driven by a clock signal. If clock and data signals are synchronized, everything works perfectly. If clock and data signals are not synchronized, then a device may sense a prior value on the data signal, or possibly even a "garbage" value. Timing verification can detect errors in a design by indicating that events are occurring too far apart or to close together to be properly synchronized. Timing verification can determine whether there are such errors in the design.
Such errors can happen intermittently or all the time. If the error happens all the time, it is often easy to correct. But, if the error happens intermittently, e.g., once or twice a year, it may create tremendous problems and be virtually impossible to correct.
When a circuit is built, an engineer will use timing verification techniques to identify such errors so that they can be eliminated. However, timing verification relies on an accurate specification of the timing relationships of all devices used in the circuit.
Unfortunately, when the circuit goes into production, many copies of individual devices are used, and the timing effect, i.e., the delay, caused by those devices will vary from copy to copy. Typically, the delay associated with a particular copy of a device will fall somewhere within some predetermined range.
Further, there may be hundred, thousands, or millions of devices within the circuit. When constructing a timing diagram of a circuit to use for verification purposes, chances are that many timing relationships need to be re-evaluated anytime the specifications of any one device is changed. This is particularly true as device and circuit speeds increase and timing margins, i.e., the amount of slack time between events, decrease.
Timing margins can often be less than one-billionth of a second. When device and circuit speeds were slower, manual methods of evaluating a circuit's operation and verifying timing relationships therein proved successful. However, with the higher speeds and more complex circuits, there is a need in the art for automated methods of circuit evaluation and verification.
The prior art includes a category of tools called Timing Analysis and Verification Software that can be used to perform circuit evaluation and verification. The two main tools in this category are called Digital Simulators and Static Timing Analyzers. Simulators and analyzers can be used for some degree of timing verification.
A simulator is typically used to test all the various logical conditions of the devices comprising the circuit. Simulators are good for verifying that a circuit works i.e., that the fundamental logic of the circuit is correct, but they are poor for determining whether the circuit will work with worst case timing variations. It is difficult to stimulate a simulator to make sure that worst case timing variations have been tried.
One reason for this is that simulators are good at treating devices having a single delay associated therewith, but they are poor at treating devices having a range of possible delays. At best, simulators set all devices to their minimum possible delay and simulate that, and then they set all devices to their maximum possible delay and simulate that. Such a test is not a true indication of circuit behavior, because, in reality, circuits are never built with all the devices at their minimum or maximum delay. Instead, circuits always have some mix of delays somewhere between their specified ranges.
Static timing analyzers are usually batch programs, i.e., there is no human intervention until after the analyzer has completed its task. Analyzers, rather than relying on stimulation of the circuit, attempt a comprehensive analysis of the circuit to test for timing problems. The input to an analyzer is a completed circuit diagram; the output of the analyzer is a list of possible timing violations. The problem with verifiers are two-fold. First, they only work with a subset of circuits called synchronous circuits. Second, they have a tendency to be overly conservative. They flag many conditions as invalid which are valid.
A problem for both simulators and analyzers, however, is that they require a model for every single device in the circuit. Such models are often non-existent and difficult to produce.
Another problem with both simulators and timing analyzers is that they cannot be used until the design of the circuit is complete. Both simulators and timing analyzers can only attempt to verify, after the fact, whether the circuit is correct; they are not design tools.
Because timing diagrams are the traditional tools used by engineers to create designs, there is a need in the art for timing verification tools which automate the entry and modification of timing diagrams. There is also a need for an automated mechanism for analyzing the timing diagrams and verifying that specified timing relationships are met using the parts selected for the design.